(2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number 74LVC04AD-Q100 Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 TSSOP14 plastic thin shrink outline package; 14 leads; body width 4.4 mm SOT402-1 74LVC04APW-Q100 40 C to +125 C 74LVC04ABQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm SOT762-1 74LVC04A-Q100 NXP Semiconductors Hex inverter 4. Functional diagram 1 1 1A 1Y 2 3 2A 2Y 4 3 5 5 3A 3Y 6 9 4A 4Y 8 11 5A 5Y 10 13 6A 6Y 12 9 11 13 2 1 4 1 6 1 8 1 10 1 12 Y A mna343 mna342 Fig 1. 1 Logic symbol Fig 2. mna341 IEC logic symbol Fig 3. Logic diagram for one gate 5. Pinning information 5.1 Pinning $ WHUPLQ
(2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number 74LVC04AD-Q100 Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 TSSOP14 plastic thin shrink outline package; 14 leads; body width 4.4 mm SOT402-1 74LVC04APW-Q100 40 C to +125 C 74LVC04ABQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm SOT762-1 74LVC04A-Q100 NXP Semiconductors Hex inverter 4. Functional diagram 1 1 1A 1Y 2 3 2A 2Y 4 3 5 5 3A 3Y 6 9 4A 4Y 8 11 5A 5Y 10 13 6A 6Y 12 9 11 13 2 1 4 1 6 1 8 1 10 1 12 Y A mna343 mna342 Fig 1. 1 Logic symbol Fig 2. mna341 IEC logic symbol Fig 3. Logic diagram for one gate 5. Pinning information 5.1 Pinning $ WHUPLQ